Integrated circuits have become larger and more complex to provide additional functionality and/or improved performance. The task of designing these integrated circuits is also very complex and time consuming, involving synthesizing, analyzing and optimizing many circuit parameters. Because of this complexity, electronic design automation (EDA) systems have been developed to assist designers in developing integrated circuit designs at multitude levels of abstraction.
To ease the design of a complex integrated circuit, design tasks may be divided up into multiple functional blocks with a plurality of levels of hierarchy. However, dividing up an integrated circuit design into multiple blocks and hierarchical levels can complicate the evaluation of the overall circuit design. Moreover an integrated circuit design may be so large in size or scale (e.g., 1 million gates or more), each partition may have numerous signal paths (e.g., hundreds of thousands of signal paths for data, address, control, and clock signals) and numerous input, output, or input/output ports (e.g., thousands of ports).
With giga gate (e.g., 1 billion gates or more) scale integrated circuit designs, robust hierarchical solutions to analyzing integrated circuit designs become even more important. Limits of computer capacity have bound chip designers to implement giga gate chip designs hierarchically. However, dividing the semiconductor chip hierarchically and implementing it through software is a complex and involved process. The added prototyping complexity involved can be justified if the implementation process yields quick turnaround times without extra iterations or repetition in the design flow process. With a giga gate chip design, hierarchical design becomes the preferred choice, but fast turnaround times in chip closure remains a factor to reckon with.
Timing budgets for data paths are usually automatically generated in early design stages when the integrated circuit design may be incomplete or have errors so that generated timing budgets may require manual correction and analysis. The process of automatic timing budgeting is usually focused on data paths and overlooks the clock paths. The timing budgeting for data paths for a partition may have assumed that the timing in the clock path would not influence the data paths. However, the load on a clock path within a partition may by significant such that the clock path also requires time budgeting across partitions.
Thus, there is a need for an apparatus, systems, and methods for time budgeting of both clock paths and data paths in hierarchical integrated circuit designs so that timing goals of an integrated circuit design may be met.